1. Technical Field
The present invention relates to semiconductor circuit technology, and more particularly, to a semiconductor integrated circuit.
2. Related Art
As a semiconductor memory is highly integrated, necessity to enhance the memory capacity of a package has increased. As a way of enhancing the memory capacity of a package, a multi-chip package is widely used.
In the multi-chip package, a plurality of semiconductor chips (hereinafter simply referred to as “chips”) should be electrically connected. Methods for electrically connecting the plurality of chips in the multi-chip package are divided into several categories, including a wire bonding type in which the plurality of chips are electrically connected using wires and a through-silicon via type in which the plurality of chips are electrically connected using silicon vias.
The plurality of chips constituting the multi-chip package are respectively tested at a wafer level using probes.
Since the chips are tested at a wafer level, signal loading at a multi-chip package level cannot be reflected.
Therefore, when the chips are tested at a wafer level, the reliability of test results is likely to deteriorate due to timing errors of signals, and the operational performance of the multi-chip package can be degraded.